1. Field of the Invention
The present invention is related to a clock reproducing apparatus. Recently, in a data transfer field, there is a need for transferring large amounts of data in high speeds. For example, such a method has been increased in which data transfer apparatuses are coupled to each other by employing optical fibers so as to transfer large amounts of data in high speeds. In this sort of transfer method, data transmitted via the optical fibers are converted into electric signals by an optical/electric converter, and thereafter, the data are reproduced. In this sort of technical field, since there are many possibilities that data are transmitted in a burst mode, a clock reproducing apparatus capable of reliably reproducing such data has been required.
2. Description of the Related Art
FIG. 20 is a block diagram for indicating a first example of a clock reproducing circuit of a related art. While this clock reproducing circuit employs a PLL (Phase-Located Loop) circuit, a clock in synchronism with input data is generated by an analog oscillator (VCO) 1 and a phase detector 2, and then, the generated clock is used as a reproduced clock. Also, a D type flip-flop (will be referred to as “DFF” hereinafter) 3 is operated by this clock so as to reproduce data.
In this clock reproducing circuit of the related art, input data (“DATA In”) is input to one input terminal of the phase detector 2, and also, input to a data input terminal of the DFF 3. An output of the phase detector 2 is amplified by an amplifier 4, and thereafter, the amplified output signal is input to the VCO 1 as a “VTUNE” signal. An output of the VCO 1 is amplified by an amplifier 5, and thereafter, the amplified signal is input to a clock input terminal of the DFF 3 and the other input terminal of the phase detector 2. Then, an output of the amplifier 5 becomes a reproduced clock, and the input data latched by this reproduced clock becomes output data (reproduced data). In the drawing, symbol “DATA out*” corresponds to an inverted output of “DATA out.”
FIG. 21 is a block diagram for indicating a second example of a clock reproducing circuit of a related art. While this clock reproducing circuit employs two oscillators 11 and 12 equipped with reset terminals, one oscillator 11 operates when input data is “H”, whereas the other oscillator 12 operates when input data is “L.” Outputs of these two oscillators 11 and 12 are added so as to reproduce a clock in synchronism with input data. Also, similar to the above-explained case of FIG. 20, a D type flip-flop (DFF) 13 is operated by this reproduced clock so as to output reproduced data.
In this circuit, as an oscillator 11 (namely, first oscillator) and another oscillator 12 (namely, second oscillator), gated oscillators are employed. This gated oscillator will also be called as a ring oscillator. Input data (DATA In) is input to a reset input terminal of the first oscillator 11, and also, input to a data input terminal of the DFF 13. The input data is inverted by an inverter 14, and thereafter, the inverted data is input to a reset input terminal of the second oscillator 12.
The output of the first oscillator 11 and the output of the second oscillator 12 are input to an OR gate 15, and are input to a frequency control circuit 16, respectively. A reference clock is also input to the input terminal of the frequency control circuit 16. Then, output signals of the frequency control circuit 16 are supplied to the first and second oscillators 11 and 12 respectively as phase control signals which are used to set delay times. In accordance with the circuit provided in the above-explained manner, the first oscillator 11 operates when the input data is “H”, the second oscillator 12 operates when the input data is “L”, and the output signals of these first and second oscillators 11 and 12 are input to the OR gate 15, so that these output signals are added to output the added signal. This output of the OR gate 15 becomes a reproduced clock (CLOCK out), and the data input to the data input terminal of the OFF 13 is latched by the reproduced clock, and then, the latched data is output as reproduced data (DATA out).
FIG. 22 is a circuit diagram for showing a configuration of the above-explained gated oscillator, and is a known circuit. A reset signal is input to one input terminal of the AND gate 21. An output of this gated oscillator is input to the other input terminal. An output of the AND gate 21 is input via a buffer 22 to a plurality of inverters 23. The plural inverters 23 are connected in a series manner, an output of the inverter 23 of a final stage is output as an output (Output), and, as previously explained, that output is fed back to the other input terminal of the AND gate 21. This circuit constitutes a positive feedback circuit as an entire circuit, and is oscillated by, for instance, a power supply being turned ON, or noise, as a trigger. A frequency control signal is input to the respective gates 22 and 23. The frequency control signal corresponds to a phase control signal for setting a delay time of the oscillating circuit. In a case where a reset input is “L”, an output of the AND gate 21 becomes “L”, so that the circuit does not operate. In a case where a reset input is “H”, an output of the AND gate 21 becomes “H”, so that the circuit functions as an oscillating circuit.
As this sort of clock reproducing apparatus, the following technical idea is known. That is, for example, in a clock reproducing apparatus for controlling a ring oscillation, and for reproducing a clock signal from a received data signal to output the reproduced clock signal, an edge portion of a delay signal of the received data signal is controlled and inverted for each of edges of the received data signal based on a phase judging signal of the clock signal, and then, the inverted delay signal is injected into a loop of the ring oscillation so as to synchronize the clock signal (refer to, for example, JP-A-2004-104522). Also, another related technical idea is known. That is, such a clock reproducing apparatus is equipped with clock reproducing means for outputting a reproduced clock, and counting means for counting the reproduced clock being output from the clock reproducing means, and the clock reproducing means selects only valid clock information from clock information received from a transmission side and reproduces clock based on the selected received clock information and the count value of the count means (refer to, for instance, JP-A-2004-179807).
In the method of using the PLL circuit shown in FIG. 20, such a problem arises that this method cannot be utilized in a case of the burst mode (namely, packet data are intermittently transmitted) and to a signal of 0/1 series in which “0” and “1” continues for long time.
On the other hand, the method of adding the outputs of the two oscillators as indicated in FIG. 21 is capable of being employed even in the burst mode. However, this clock reproducing method owns the following problem. That is, in a case of such a high speed communication which is higher than or equal to 10 Gbps, when “0” and “1” are input, oscillation cannot be performed well, and stable operation of the circuit can be hardly realized.